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Electronics Engineering · IIT (BHU), Varanasi ·

Niraj N.
Hariyani

Digital Hardware & Verilog Design
Student Executive, Student Alumni Interaction Cell (SAIC), IIT (BHU), Varanasi.

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01 — About

Building at the circuit level

-year Electronics Engineering student at IIT (BHU), Varanasi. My work sits at the intersection of digital hardware and systems thinking; writing RTL in Verilog, implementing logic on FPGAs, and understanding how software-described behaviour translates to actual gates and wires on silicon.

I'm drawn to the clarity of hardware: when you write HDL, there is no ambiguity about what the machine does. That precision keeps pulling me deeper into architectural designs, synthesis workflows and physical designs.

Alongside the technical side, I co-founded DeckIt and am a Student Executive at SAIC, curious about how ideas become organizations, and how engineering knowledge applies at the product level.

Technical Skills

Verilog / VHDLFPGA DesignXilinx VivadoDigital ElectronicsRTL DesignComputer ArchitectureVLSI / GDSIIC++Python

Leadership & Other

FoundingLeadershipMentorshipProduct Strategy
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Years at IIT
0
HW Projects
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National Awards
0
Active Roles
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Years at IIT (BHU)
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Hardware Projects
0
National Awards
0
Active Roles

02 — Experience

Roles & Responsibilities

Student Alumni Interaction Cell
IIT (BHU), Varanasi
Student Executive, SAIC

Part of the Student Alumni Interaction Cell at IIT (BHU), Varanasi organizing alumni engagement events, facilitating mentorship connections, and strengthening the student-alumni network across batches.

Student Counselling Services
IIT (BHU), Varanasi
Induction Mentor

Selected through a competitive process to guide first-year students through IIT (BHU)'s induction, helping navigate academic expectations, campus culture, and the adjustment the first semester at an IIT demands.

DeckIt, Self-employed
Varanasi
Founding Member

Co-founded DeckIt from scratch in Varanasi. The one-stop for all National and Internationally winning decks.

03 — Work

Selected Projects

001
FPGA-Based FFT Engine for Edge Detection
Implemented the Single-Delay Feedback Architecture for Fast Fourier Transform and designed a fully pipelined, parameterised architecture for streaming edge detection on FPGA.
VerilogXilinx VivadoRTL Synthesis
002
FFT ASIC Design
Designed a physical IC following the complete RTL-to-GDSII flow, including floorplanning, static timing analysis, routing, and placement on OpenROAD.
OpenROADVerilogSTAGDSII
003
Deterministic Spatial Intelligence Engine
Designed a hardware accelerator that processes 2D spatial point data stored in EEPROM to identify the closest pair and compute a hardware-friendly spatial metric in a fully deterministic manner.
FSMVerilogSequential Logic
004
DeckIt — Product Strategy & Formation
Co-founded DeckIt from concept validation through team formation and early product positioning. Ongoing build at the intersection of engineering and product thinking.
Product StrategyFoundingGo-to-Market

04 — Recognition

Honours & Awards

01
Case-O-Nova · MaShIIM Bangalore
3rd Runner Up — National Marketing Competition
4th place among 1800+ national participants. GTM strategy for SUGAR Cosmetics vs L'Oreal. The only IIT team in the finals, competing against India's top management institutes.
Mar 2025 · MaSh, IIM Bangalore
02
Prodnosis · Technex 2025IIT (BHU), Varanasi
National Winner — Product Management Competition
First place nationally at Technex, IIT (BHU)'s techno-management fest. Full product strategy and go-to-market plan presented to a national panel of judges.
Mar 2025 · Technex, IIT (BHU)
03
ADVENTURE · E-Summit 2025IIT (BHU), Varanasi
1st Runner Up — Branding Challenge
2nd prize at E-Cell, IIT (BHU). Built a complete marketing strategy for "Sochu," a children's educational bookselling platform, under live competition conditions.
Mar 2025 · E-Cell, IIT (BHU)
Verilog & Digital Design / FPGA Design / DeckIt Founding Member / SAIC Student Executive / IIM Bangalore Finalist / National Case Winner / RTL-to-GDSII Flow / IIT (BHU), Varanasi / Induction Mentor / Verilog & Digital Design / FPGA Design / DeckIt Founding Member / SAIC Student Executive / IIM Bangalore Finalist / National Case Winner / RTL-to-GDSII Flow / IIT (BHU), Varanasi / Induction Mentor /

05 — Education

Academic Background

Indian Institute of Technology (BHU), Varanasi
B.Tech, Electronics Engineering — Digital Electronics, Verilog, FPGA, VLSI
Intermediate
Intermediate
St. Paul Jr. College, Nagpur
PCM with Computer Science (C++)
86.17%
Matriculation
Matriculation
St. Anne's Public School
PCM
98.2%

06 — Contact

Let's talk.

Open to internships, research roles, and genuine conversations about digital hardware, FPGA, product thinking, or anything at the intersection of circuits and ideas.

Reach me at